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* Update Verilog courses Renamed `SystemVerilog` section to `Verilog / VHDL / SystemVerilog` because they are 3 different hardware description languages. Grouped them together so that all the Verilog resources can be found in one spot. Added new course as suggested in #2151 * Reorder Verilog courses by alphabetical order * Add new course suggested by @mramdas * Reorder Verilog courses
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* [Scala](#scala)
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* [Software Engineering](#software-engineering)
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* [Swift](#swift)
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* [SystemVerilog](#systemverilog)
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* [Theory](#theory)
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* [Verilog / VHDL / SystemVerilog](#verilog--vhdl--systemverilog)
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* [Web Development](#web-development)
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* [Swiftris - Build an iOS Tetris app from scratch](https://www.bloc.io/swiftris-build-your-first-ios-game-with-swift)
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### SystemVerilog
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* [SystemVerilog - Learn basics of SystemVerilog for Hardware Verification](https://verificationexcellence.teachable.com/p/learn-systemverilog)
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* [SystemVerilog based UVM Methodology - Learn to build UVM based Testbenches in SystemVerilog](https://verificationexcellence.teachable.com/p/learn-ovm-uvm)
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### Theory
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* [Automata Theory](https://lagunita.stanford.edu/courses/course-v1:ComputerScience+Automata+Fall2016/about)
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* [Udacity: Intro to Theoretical Computer Science](https://www.udacity.com/course/intro-to-theoretical-computer-science--cs313)
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### Verilog / VHDL / SystemVerilog
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* [SOC Verification Using SystemVerilog](http://verificationexcellence.in/online-courses/soc-verification-using-systemverilog)
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* [SystemVerilog - Learn basics of SystemVerilog for Hardware Verification](https://verificationexcellence.teachable.com/p/learn-systemverilog)
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* [SystemVerilog based UVM Methodology - Learn to build UVM based Testbenches in SystemVerilog](https://verificationexcellence.teachable.com/p/learn-ovm-uvm)
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* [Verilog Hardware Description Language - An Introductory Course](http://vol.verilog.com/VOL/main.htm)
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### Web Development
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* [Discover Flask - Full Stack Web Development with Flask](https://github.com/realpython/discover-flask)
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