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Update with SystemVerilog FREE courses (#2248)

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* Update with SystemVerilog FREE courses

SystemVerilog is IEEE1800 standard and most widely used Hardware Description language

* Update with SystemVerilog FREE course

Update with SystemVerilog (IEEE1800 standard and commonly used Hardware Description Language)
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Ramdas M 2017-02-04 16:02:02 +05:30 committed by victor felder
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@ -34,6 +34,7 @@
* [Scala](#scala) * [Scala](#scala)
* [Software Engineering](#software-engineering) * [Software Engineering](#software-engineering)
* [Swift](#swift) * [Swift](#swift)
* [SystemVerilog](#systemverilog)
* [Theory](#theory) * [Theory](#theory)
* [Web Development](#web-development) * [Web Development](#web-development)
@ -284,6 +285,12 @@
* [Swiftris - Build an iOS Tetris app from scratch](https://www.bloc.io/swiftris-build-your-first-ios-game-with-swift) * [Swiftris - Build an iOS Tetris app from scratch](https://www.bloc.io/swiftris-build-your-first-ios-game-with-swift)
### SystemVerilog
* [SystemVerilog - Learn basics of SystemVerilog for Hardware Verification](https://verificationexcellence.teachable.com/p/learn-systemverilog)
* [SystemVerilog based UVM Methodology - Learn to build UVM based Testbenches in SystemVerilog](https://verificationexcellence.teachable.com/p/learn-ovm-uvm)
### Theory ### Theory
* [Automata Theory](https://lagunita.stanford.edu/courses/course-v1:ComputerScience+Automata+Fall2016/about) * [Automata Theory](https://lagunita.stanford.edu/courses/course-v1:ComputerScience+Automata+Fall2016/about)