mirror of
https://github.com/octoleo/restic.git
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291 lines
8.5 KiB
ArmAsm
291 lines
8.5 KiB
ArmAsm
// Copyright 2016 The Go Authors. All rights reserved.
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// Use of this source code is governed by a BSD-style
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// license that can be found in the LICENSE file.
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// +build amd64,!gccgo,!appengine
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#include "textflag.h"
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DATA ·iv0<>+0x00(SB)/8, $0x6a09e667f3bcc908
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DATA ·iv0<>+0x08(SB)/8, $0xbb67ae8584caa73b
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GLOBL ·iv0<>(SB), (NOPTR+RODATA), $16
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DATA ·iv1<>+0x00(SB)/8, $0x3c6ef372fe94f82b
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DATA ·iv1<>+0x08(SB)/8, $0xa54ff53a5f1d36f1
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GLOBL ·iv1<>(SB), (NOPTR+RODATA), $16
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DATA ·iv2<>+0x00(SB)/8, $0x510e527fade682d1
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DATA ·iv2<>+0x08(SB)/8, $0x9b05688c2b3e6c1f
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GLOBL ·iv2<>(SB), (NOPTR+RODATA), $16
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DATA ·iv3<>+0x00(SB)/8, $0x1f83d9abfb41bd6b
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DATA ·iv3<>+0x08(SB)/8, $0x5be0cd19137e2179
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GLOBL ·iv3<>(SB), (NOPTR+RODATA), $16
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DATA ·c40<>+0x00(SB)/8, $0x0201000706050403
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DATA ·c40<>+0x08(SB)/8, $0x0a09080f0e0d0c0b
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GLOBL ·c40<>(SB), (NOPTR+RODATA), $16
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DATA ·c48<>+0x00(SB)/8, $0x0100070605040302
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DATA ·c48<>+0x08(SB)/8, $0x09080f0e0d0c0b0a
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GLOBL ·c48<>(SB), (NOPTR+RODATA), $16
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#define SHUFFLE(v2, v3, v4, v5, v6, v7, t1, t2) \
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MOVO v4, t1; \
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MOVO v5, v4; \
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MOVO t1, v5; \
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MOVO v6, t1; \
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PUNPCKLQDQ v6, t2; \
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PUNPCKHQDQ v7, v6; \
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PUNPCKHQDQ t2, v6; \
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PUNPCKLQDQ v7, t2; \
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MOVO t1, v7; \
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MOVO v2, t1; \
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PUNPCKHQDQ t2, v7; \
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PUNPCKLQDQ v3, t2; \
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PUNPCKHQDQ t2, v2; \
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PUNPCKLQDQ t1, t2; \
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PUNPCKHQDQ t2, v3
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#define SHUFFLE_INV(v2, v3, v4, v5, v6, v7, t1, t2) \
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MOVO v4, t1; \
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MOVO v5, v4; \
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MOVO t1, v5; \
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MOVO v2, t1; \
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PUNPCKLQDQ v2, t2; \
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PUNPCKHQDQ v3, v2; \
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PUNPCKHQDQ t2, v2; \
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PUNPCKLQDQ v3, t2; \
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MOVO t1, v3; \
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MOVO v6, t1; \
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PUNPCKHQDQ t2, v3; \
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PUNPCKLQDQ v7, t2; \
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PUNPCKHQDQ t2, v6; \
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PUNPCKLQDQ t1, t2; \
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PUNPCKHQDQ t2, v7
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#define HALF_ROUND(v0, v1, v2, v3, v4, v5, v6, v7, m0, m1, m2, m3, t0, c40, c48) \
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PADDQ m0, v0; \
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PADDQ m1, v1; \
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PADDQ v2, v0; \
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PADDQ v3, v1; \
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PXOR v0, v6; \
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PXOR v1, v7; \
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PSHUFD $0xB1, v6, v6; \
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PSHUFD $0xB1, v7, v7; \
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PADDQ v6, v4; \
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PADDQ v7, v5; \
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PXOR v4, v2; \
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PXOR v5, v3; \
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PSHUFB c40, v2; \
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PSHUFB c40, v3; \
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PADDQ m2, v0; \
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PADDQ m3, v1; \
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PADDQ v2, v0; \
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PADDQ v3, v1; \
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PXOR v0, v6; \
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PXOR v1, v7; \
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PSHUFB c48, v6; \
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PSHUFB c48, v7; \
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PADDQ v6, v4; \
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PADDQ v7, v5; \
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PXOR v4, v2; \
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PXOR v5, v3; \
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MOVOU v2, t0; \
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PADDQ v2, t0; \
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PSRLQ $63, v2; \
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PXOR t0, v2; \
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MOVOU v3, t0; \
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PADDQ v3, t0; \
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PSRLQ $63, v3; \
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PXOR t0, v3
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#define LOAD_MSG(m0, m1, m2, m3, src, i0, i1, i2, i3, i4, i5, i6, i7) \
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MOVQ i0*8(src), m0; \
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PINSRQ $1, i1*8(src), m0; \
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MOVQ i2*8(src), m1; \
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PINSRQ $1, i3*8(src), m1; \
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MOVQ i4*8(src), m2; \
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PINSRQ $1, i5*8(src), m2; \
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MOVQ i6*8(src), m3; \
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PINSRQ $1, i7*8(src), m3
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// func hashBlocksSSE4(h *[8]uint64, c *[2]uint64, flag uint64, blocks []byte)
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TEXT ·hashBlocksSSE4(SB), 4, $288-48 // frame size = 272 + 16 byte alignment
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MOVQ h+0(FP), AX
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MOVQ c+8(FP), BX
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MOVQ flag+16(FP), CX
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MOVQ blocks_base+24(FP), SI
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MOVQ blocks_len+32(FP), DI
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MOVQ SP, BP
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MOVQ SP, R9
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ADDQ $15, R9
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ANDQ $~15, R9
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MOVQ R9, SP
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MOVOU ·iv3<>(SB), X0
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MOVO X0, 0(SP)
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XORQ CX, 0(SP) // 0(SP) = ·iv3 ^ (CX || 0)
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MOVOU ·c40<>(SB), X13
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MOVOU ·c48<>(SB), X14
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MOVOU 0(AX), X12
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MOVOU 16(AX), X15
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MOVQ 0(BX), R8
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MOVQ 8(BX), R9
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loop:
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ADDQ $128, R8
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CMPQ R8, $128
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JGE noinc
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INCQ R9
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noinc:
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MOVQ R8, X8
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PINSRQ $1, R9, X8
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MOVO X12, X0
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MOVO X15, X1
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MOVOU 32(AX), X2
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MOVOU 48(AX), X3
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MOVOU ·iv0<>(SB), X4
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MOVOU ·iv1<>(SB), X5
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MOVOU ·iv2<>(SB), X6
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PXOR X8, X6
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MOVO 0(SP), X7
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LOAD_MSG(X8, X9, X10, X11, SI, 0, 2, 4, 6, 1, 3, 5, 7)
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MOVO X8, 16(SP)
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MOVO X9, 32(SP)
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MOVO X10, 48(SP)
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MOVO X11, 64(SP)
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HALF_ROUND(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14)
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SHUFFLE(X2, X3, X4, X5, X6, X7, X8, X9)
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LOAD_MSG(X8, X9, X10, X11, SI, 8, 10, 12, 14, 9, 11, 13, 15)
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MOVO X8, 80(SP)
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MOVO X9, 96(SP)
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MOVO X10, 112(SP)
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MOVO X11, 128(SP)
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HALF_ROUND(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14)
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SHUFFLE_INV(X2, X3, X4, X5, X6, X7, X8, X9)
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LOAD_MSG(X8, X9, X10, X11, SI, 14, 4, 9, 13, 10, 8, 15, 6)
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MOVO X8, 144(SP)
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MOVO X9, 160(SP)
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MOVO X10, 176(SP)
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MOVO X11, 192(SP)
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HALF_ROUND(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14)
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SHUFFLE(X2, X3, X4, X5, X6, X7, X8, X9)
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LOAD_MSG(X8, X9, X10, X11, SI, 1, 0, 11, 5, 12, 2, 7, 3)
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MOVO X8, 208(SP)
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MOVO X9, 224(SP)
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MOVO X10, 240(SP)
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MOVO X11, 256(SP)
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HALF_ROUND(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14)
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SHUFFLE_INV(X2, X3, X4, X5, X6, X7, X8, X9)
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LOAD_MSG(X8, X9, X10, X11, SI, 11, 12, 5, 15, 8, 0, 2, 13)
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HALF_ROUND(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14)
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SHUFFLE(X2, X3, X4, X5, X6, X7, X8, X9)
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LOAD_MSG(X8, X9, X10, X11, SI, 10, 3, 7, 9, 14, 6, 1, 4)
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HALF_ROUND(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14)
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SHUFFLE_INV(X2, X3, X4, X5, X6, X7, X8, X9)
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LOAD_MSG(X8, X9, X10, X11, SI, 7, 3, 13, 11, 9, 1, 12, 14)
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HALF_ROUND(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14)
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SHUFFLE(X2, X3, X4, X5, X6, X7, X8, X9)
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LOAD_MSG(X8, X9, X10, X11, SI, 2, 5, 4, 15, 6, 10, 0, 8)
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HALF_ROUND(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14)
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SHUFFLE_INV(X2, X3, X4, X5, X6, X7, X8, X9)
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LOAD_MSG(X8, X9, X10, X11, SI, 9, 5, 2, 10, 0, 7, 4, 15)
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HALF_ROUND(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14)
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SHUFFLE(X2, X3, X4, X5, X6, X7, X8, X9)
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LOAD_MSG(X8, X9, X10, X11, SI, 14, 11, 6, 3, 1, 12, 8, 13)
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HALF_ROUND(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14)
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SHUFFLE_INV(X2, X3, X4, X5, X6, X7, X8, X9)
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LOAD_MSG(X8, X9, X10, X11, SI, 2, 6, 0, 8, 12, 10, 11, 3)
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HALF_ROUND(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14)
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SHUFFLE(X2, X3, X4, X5, X6, X7, X8, X9)
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LOAD_MSG(X8, X9, X10, X11, SI, 4, 7, 15, 1, 13, 5, 14, 9)
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HALF_ROUND(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14)
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SHUFFLE_INV(X2, X3, X4, X5, X6, X7, X8, X9)
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LOAD_MSG(X8, X9, X10, X11, SI, 12, 1, 14, 4, 5, 15, 13, 10)
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HALF_ROUND(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14)
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SHUFFLE(X2, X3, X4, X5, X6, X7, X8, X9)
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LOAD_MSG(X8, X9, X10, X11, SI, 0, 6, 9, 8, 7, 3, 2, 11)
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HALF_ROUND(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14)
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SHUFFLE_INV(X2, X3, X4, X5, X6, X7, X8, X9)
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LOAD_MSG(X8, X9, X10, X11, SI, 13, 7, 12, 3, 11, 14, 1, 9)
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HALF_ROUND(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14)
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SHUFFLE(X2, X3, X4, X5, X6, X7, X8, X9)
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LOAD_MSG(X8, X9, X10, X11, SI, 5, 15, 8, 2, 0, 4, 6, 10)
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HALF_ROUND(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14)
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SHUFFLE_INV(X2, X3, X4, X5, X6, X7, X8, X9)
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LOAD_MSG(X8, X9, X10, X11, SI, 6, 14, 11, 0, 15, 9, 3, 8)
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HALF_ROUND(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14)
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SHUFFLE(X2, X3, X4, X5, X6, X7, X8, X9)
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LOAD_MSG(X8, X9, X10, X11, SI, 12, 13, 1, 10, 2, 7, 4, 5)
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HALF_ROUND(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14)
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SHUFFLE_INV(X2, X3, X4, X5, X6, X7, X8, X9)
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LOAD_MSG(X8, X9, X10, X11, SI, 10, 8, 7, 1, 2, 4, 6, 5)
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HALF_ROUND(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14)
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SHUFFLE(X2, X3, X4, X5, X6, X7, X8, X9)
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LOAD_MSG(X8, X9, X10, X11, SI, 15, 9, 3, 13, 11, 14, 12, 0)
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HALF_ROUND(X0, X1, X2, X3, X4, X5, X6, X7, X8, X9, X10, X11, X11, X13, X14)
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SHUFFLE_INV(X2, X3, X4, X5, X6, X7, X8, X9)
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HALF_ROUND(X0, X1, X2, X3, X4, X5, X6, X7, 16(SP), 32(SP), 48(SP), 64(SP), X11, X13, X14)
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SHUFFLE(X2, X3, X4, X5, X6, X7, X8, X9)
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HALF_ROUND(X0, X1, X2, X3, X4, X5, X6, X7, 80(SP), 96(SP), 112(SP), 128(SP), X11, X13, X14)
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SHUFFLE_INV(X2, X3, X4, X5, X6, X7, X8, X9)
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HALF_ROUND(X0, X1, X2, X3, X4, X5, X6, X7, 144(SP), 160(SP), 176(SP), 192(SP), X11, X13, X14)
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SHUFFLE(X2, X3, X4, X5, X6, X7, X8, X9)
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HALF_ROUND(X0, X1, X2, X3, X4, X5, X6, X7, 208(SP), 224(SP), 240(SP), 256(SP), X11, X13, X14)
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SHUFFLE_INV(X2, X3, X4, X5, X6, X7, X8, X9)
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MOVOU 32(AX), X10
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MOVOU 48(AX), X11
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PXOR X0, X12
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PXOR X1, X15
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PXOR X2, X10
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PXOR X3, X11
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PXOR X4, X12
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PXOR X5, X15
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PXOR X6, X10
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PXOR X7, X11
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MOVOU X10, 32(AX)
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MOVOU X11, 48(AX)
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LEAQ 128(SI), SI
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SUBQ $128, DI
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JNE loop
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MOVOU X12, 0(AX)
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MOVOU X15, 16(AX)
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MOVQ R8, 0(BX)
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MOVQ R9, 8(BX)
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MOVQ BP, SP
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RET
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// func supportsSSE4() bool
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TEXT ·supportsSSE4(SB), 4, $0-1
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MOVL $1, AX
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CPUID
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SHRL $19, CX // Bit 19 indicates SSE4 support
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ANDL $1, CX // CX != 0 if support SSE4
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MOVB CX, ret+0(FP)
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RET
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